import chisel3._
import chisel3.util._

class Max3 extends Module {
  val io = IO(new Bundle {
    val in_a = Input(UInt(16.W))
    val in_b = Input(UInt(16.W))
    val in_c = Input(UInt(16.W))
    val out  = Output(UInt(16.W))
  })

  when(io.in_a >= io.in_b && io.in_a >= io.in_c) {
    io.out := io.in_a
  }.elsewhen(io.in_b >= io.in_c) {
    io.out := io.in_b
  }.otherwise {
    io.out := io.in_c
  }
}

object Max3 extends App {
  println(getVerilogString(new Max3()))
}
